Random access memory, or RAM, comprises a key part of virtually every processor-based system. Numerous different RAM designs have been tried and found market acceptance. Recently, high density static RAM designs have been developed for use in workstations, personal computers, embedded systems and supercomputer main memory. As higher performance has been demanded by the application, various improvements to SRAM design have been developed, including synchronous wave-pipeline SRAM.
However, regardless of the type of RAM used, the data delay is still determined by the critical path from the address input to the data output. This path includes the address buffer, the input register, the decoder, the addressed memory cell, the sense amplifier, the output register and the output buffer.
New designs most commonly are intended to improve performance, either through reducing the delay time in the various stages, or to reduce either cost or power. One effective way to reduce cost is to reduce die size. Reductions in die size can be achieved either by improving the circuit or improving layout efficiency, or both. Power reductions can be achieved by reducing sense amplifier current or other techniques.
Various prior art designs have attempted to reduce sense amplifier current or otherwise improve sense amplifier performance. Several such designs are described in U.S. Pat. Nos. 5,544,110; 5,566,126; 5,526,314; 5,297,092; 5,294,847; 5,289,415; and 5,231,318. The basic operation of a sense amplifier in such a circuit includes not only the basic amplifier function, but also output latching and level shifting. In addition, a desirable design feature is to provide full swing at the outputs of the amplifier. These various functions are typically performed in multiple stages, as can be seen from the aforementioned patents, but as will be apparent from a review of these patents, attempting to incorporate these features has met with limited success and, in at least some instances such as the '110 and '126 patents, has led to complicated designs which increase the layout area or otherwise cause layout problems, and are therefore difficult to manufacture. In other instances, such as the '318 patent, the output is not permitted a full swing and remain sensitive to process variations. The '092 also presents serious design limitations, including the die area required for the two stage design, the need for precharging, and the fact that erroneous data can be latched. Likewise, the '847 patent presents problems with the amount of layout area needed for the excessive number of transistors in the design, the complicated control circuit, and the multiple stages. The '314 is also overly complicated and thus requires excessive layout area, as well as requiring precharging and presenting the possibility of latching the wrong data. A three stage amplifier is used in the '415 patent, which by itself leads to a complicated layout using excessive die area; in addition, the design suffers from excessive sensitivity during the clock high period.
As a result, there has been a need for a sense amplifier which offers small die area, low power consumption, positive latching, a full voltage swing at the outputs, and an uncomplicated design.